Title :
Real-time FPGA rectification implementation combined with stereo camera
Author :
Junwon Mun ; Jaeseok Kim
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. of Yonsei, Seoul, South Korea
Abstract :
In this paper, we proposed real-time FPGA-based rectification algorithm implementation combined with stereo camera. Rectification is a necessary pre-required step for stereo matching to align left and right images, including correction of radial distortion. In our experiment, we implemented rectification module in the FPGA combined with stereo camera to verify in video circumstance. As a result, rectification for HD image is processed at 45 fps, with Zynq7020 FPGA.
Keywords :
field programmable gate arrays; high definition video; image matching; stereo image processing; video cameras; HD image; radial distortion correction; real-time FPGA-based rectification algorithm implementation; stereo camera; stereo image matching; video circumstance; Cameras; Clocks; Field programmable gate arrays; Interpolation; Random access memory; Real-time systems; Synchronization; FPGA; Rectification; Stereo Vision;
Conference_Titel :
Consumer Electronics (ISCE), 2015 IEEE International Symposium on
Conference_Location :
Madrid
DOI :
10.1109/ISCE.2015.7177765
