Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

Examines the effectiveness of opportunistic use of reverse body bias (RBB) to reduce leakage power during active operation, burn-in, and standby in 0.18 μm single-V_t and 0.13 μm dual-V_t logic process technologies. Investigates its dependencies on channel length, target V_t, temperature and technology generation. Shows that RBB becomes less effective for leakage reduction at shorter channel lengths and lower V_t at both high and room temperatures, especially when target intrinsic leakage currents are high. RBB effectiveness also diminishes with technology scaling primarily because of worsening short-channel effects (SCE), particularly when target V_t values are low. A model is given that relates different transistor leakage components to full-chip leakage current, and is validated through test-chip measurements across a range of RBB values