DocumentCode :
3410803
Title :
Maximum voltage variation in the power distribution network of VLSI circuits with RLC models
Author :
Bobba, Sudhakar ; Hajj, Ibrahim N.
Author_Institution :
Sun Microsystems Inc, Palo Alto, CA, USA
fYear :
2001
fDate :
2001
Firstpage :
376
Lastpage :
381
Abstract :
In this paper, we present a frequency-domain technique to estimate the worst-case time-domain voltage variation using RLC models for the power distribution network. The proposed method, unlike existing simulation-based techniques, can handle frequency-dependent RLC parameters and generate an upperbound on the maximum voltage drop over all possible input excitations. Pattern independent maximum envelope currents are used to estimate the upperbound on the maximum magnitude of the frequency components for the current waveform. These values are used to formulate a nonlinear optimization problem for the maximum voltage drop at nodes in the power distribution network. We then present a method to solve the nonlinear optimization problem using Lagrange multipliers. Comparisons with SPICE simulations are presented to validate the techniques presented in the paper
Keywords :
SPICE; VLSI; circuit optimisation; frequency-domain analysis; integrated circuit modelling; power supply circuits; Lagrange multiplier; RLC model; SPICE simulation; VLSI circuit; envelope current; frequency-domain technique; maximum voltage drop; nonlinear optimization; power distribution network; time-domain voltage variation; Analytical models; Delay; Frequency estimation; Intelligent networks; Power supplies; Power systems; RLC circuits; Time domain analysis; Very large scale integration; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, International Symposium on, 2001.
Conference_Location :
Huntington Beach, CA
Print_ISBN :
1-58113-371-5
Type :
conf
DOI :
10.1109/LPE.2001.945435
Filename :
945435
Link To Document :
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