Title :
A 56-bit self-timed adder for high speed asynchronous datapath
Author :
Corsonello, Pasquale ; Perri, Stefania ; Cocorullo, Giuseppe
Author_Institution :
Dept. of Electron. Eng. & Appl. Math., Univ. of Reggio Calabria, Italy
Abstract :
The most basic element in any data-path is the adder. Variable-time adders can take advantage of the shorter carry propagation chains that occur in practice and exhibit an operand dependent addition time. Such adders are useful in self-timed data-paths. Today the latter are widely used as they can compute in mean time, reduce power consumption, and avoid long clock connections. In this paper, a new high-performance variable-time adder based on the statistical carry look-ahead addition technique is presented. The new circuit uses carry select stages to reduce the critical path. A 56-bit adder designed in this way and realised with 0.5 μm CMOS technology shows an average addition time of ~1.28 ns, requiring only ~2900 transistors
Keywords :
CMOS logic circuits; adders; asynchronous circuits; high-speed integrated circuits; 0.5 micron; 1.28 ns; 56 bit; addition time; carry propagation chains; high speed asynchronous datapath; operand dependent addition time; power consumption; self-timed adder; self-timed data-paths; statistical carry look-ahead addition technique; variable-time adders; Adders; CMOS technology; Circuits; Clocks; Computer science; Data engineering; Delay; Digital systems; Lab-on-a-chip; Mathematics;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.812218