DocumentCode
3411489
Title
PowerPC 970 in 130 nm and 90 nm technologies
Author
Rohrer, N.J. ; Canada, M. ; Cohen, Emmanuel ; Ringler, M. ; Sandon, P. ; Kartschoke, P. ; Heaslip, J. ; Allen, John ; McCormick, Patrick ; Pfluger, T. ; Zimmerman, Jeramy ; Lichtenau, C. ; Werner, T. ; Salem, Gerard ; Ross, M. ; Thygesen, D.
Author_Institution
IBM Corp., Essex Junction, VT, USA
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
68
Abstract
A 64 b PowerPC microprocessor is introduced in 130 nm and redesigned in 90 nm SOI technology. PowerPC 970 implements a SIMD instruction set with 512 kB L2 cache. It runs at 2.0 GHz with a 1.0 GHz bus in 130 nm. The 90 nm design features PowerTune for rapid frequency and power scaling and electronic fuses.
Keywords
cache storage; circuit tuning; electric fuses; integrated circuit design; integrated memory circuits; microprocessor chips; parallel processing; silicon-on-insulator; 1.0 GHz; 130 nm; 2 GHz; 512 kB; 64 bit; 90 nm; L2 cache; PowerPC 970; PowerPC microprocessor; PowerPC technologies; PowerTune; SIMD instruction set; SOI technology; Si-SiO2; electronic fuses; power scaling; rapid frequency scaling; Bandwidth; Copper; Delay; Design optimization; Libraries; Logic; Microprocessors; Pipelines; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332597
Filename
1332597
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