Title :
A 10μs fast switching PLL synthesizer for a GSM/EDGE base-station
Author :
Keaveney, M. ; Walsh, Paul ; Tuthill, M. ; Hunt, B.
Author_Institution :
Analog Devices, Limerick, Ireland
Abstract :
A fractional-N PLL synthesizer with 10 μs lock time, 0.25° rms phase error, and -100 dBc/Hz in-band phase noise, suitable for GSM/EDGE base-stations, is implemented in 2.29×2.32mm2 using a 0.35 μm BiCMOS process. Up/down mismatch from the PFD (phase frequency detector) to the differential charge pump´s outputs is eliminated via a chopping scheme that permits full use of bandwidth switching.
Keywords :
BiCMOS integrated circuits; UHF integrated circuits; cellular radio; choppers (circuits); frequency synthesizers; phase detectors; phase locked loops; phase noise; 0.35 micron; 10 mus; 2.29 mm; 2.32 mm; BiCMOS; EDGE base-station; GSM; PFD up/down mismatch; bandwidth switching; chopping scheme; differential charge pump; fast switching PLL synthesizer; fractional-N PLL synthesizer; in-band phase noise; lock time; phase error; phase frequency detector; Charge pumps; Filters; Frequency synthesizers; GSM; Phase frequency detector; Phase locked loops; Phase noise; Pulse modulation; Switches; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332659
