Title :
An 800MHz embedded DRAM with a concurrent refresh mode
Author :
Kirihata, Toshiaki ; Parries, P. ; Hanson, D. ; Kim, Heonhwan ; Golz, John ; Fredeman, G. ; Rajeevakumar, R. ; Griesemer, J. ; Robson, Norman ; Cestero, Albert ; Wordeman, M. ; Iyer, Srikrishna
Author_Institution :
IBM Microelectron., Hopewell Junction, NY, USA
Abstract :
The embedded DRAM employs a transfer gate formed from a 22A Gox, 1.5V logic IO device resulting in 3.2ns cycle and latency. A concurrent refresh mode and a refresh scheduler prove ≥:99% memory availability for a 64μs cell retention time. In-macro circuitry supports redundancy allocation during 800MHz multi-banking operation.
Keywords :
DRAM chips; cellular arrays; embedded systems; low-power electronics; redundancy; 1.5 V; 800 MHz; command multiplier; concurrent refresh mode; deep trench storage capacitor; embedded DRAM; in-macro circuitry; memory availability; multi-banking operation; redundancy allocation; refresh scheduler; transfer gate; Analytical models; Capacitors; Clocks; Counting circuits; Logic arrays; Logic devices; Microelectronics; Random access memory; Signal design; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332666
