Title :
ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits
Author :
Dutta, Santanu ; Nag, Sudip ; Roy, Kaushik
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
fDate :
30 May-2 Jun 1994
Abstract :
This paper introduces an automated transistor sizing tool (ASAP) that incorporates accurate gate-level functional models and can be used for delay, area, and power optimization of CMOS combinational logic circuits in a VLSI design environment. The optimization technique is based on simulated annealing and considers the performance improvement of VLSI circuits by optimally sizing the transistors on the N most critical paths
Keywords :
CMOS logic circuits; VLSI; circuit CAD; circuit optimisation; combinational circuits; integrated circuit design; logic CAD; simulated annealing; ASAP; VLSI design environment; area optimization; automated transistor sizing tool; combinational logic circuits; gate-level functional models; most critical paths; performance improvement; power optimization; simulated annealing; speed optimization; static CMOS circuits; Circuit synthesis; Coupling circuits; Delay effects; Drives; Inverters; Large-scale systems; Power dissipation; Semiconductor device modeling; Switching circuits; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.408755
