Title :
155.52 Mbits/s parallel frame synchronous scheme for SDH networks
Author :
Teng, Jun ; Li, Lei-min ; Obaidat, M.S.
Author_Institution :
Dept. of Electr. Eng., City Univ. of New York, NY, USA
Abstract :
This paper presents an entirely novel parallel processing based frame synchronous system for 155.520 Mbps high speed networks according to the CCITT recommendations G.707, G.708 and G.709. This scheme is expected to relax operating speed requirements of the circuits used in the system. The proposed methodology can be implemented using off-the-shelf low-rate integrated circuits (ICs). The performance of the devised methodology is analyzed and found to be similar to that of the traditional approaches. Finally, the proposed scheme is efficient, easy to implement at low cost without sacrificing performance
Keywords :
B-ISDN; digital communication; logic arrays; parallel architectures; synchronisation; synchronous digital hierarchy; telecommunication standards; 155.52 Mbit/s; CCITT recommendations; G.707; G.708; G.709; SDH networks; high speed networks; low-rate integrated circuits; operating speed; parallel frame synchronous scheme; parallel processing; Cities and towns; Digital communication; Educational institutions; High-speed networks; Integrated circuit reliability; Performance analysis; Power capacitors; SONET; Synchronous digital hierarchy; Timing;
Conference_Titel :
Computers and Communications, 1996., Conference Proceedings of the 1996 IEEE Fifteenth Annual International Phoenix Conference on
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-7803-3255-5
DOI :
10.1109/PCCC.1996.493652
