DocumentCode :
3413376
Title :
Three-dimensional field-programmable gate arrays
Author :
Alexander, Michael J. ; Cohoon, James P. ; Colflesh, Jared L. ; Karro, John ; Robins, Gabriel
Author_Institution :
Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
fYear :
1995
fDate :
18-22 Sep 1995
Firstpage :
253
Lastpage :
256
Abstract :
Motivated by improving FPGA performance, we propose a new three-dimensional (3D) FPGA architecture, along with a fabrication methodology. We analyze the expected manufacturing yield, and raise several physical-design issues in the new 3D paradigm. Our techniques also have good implications for resource utilization, physical size, and power consumption
Keywords :
VLSI; application specific integrated circuits; field programmable gate arrays; integrated circuit design; integrated circuit yield; logic CAD; logic partitioning; network routing; 3D field-programmable gate arrays; 3D paradigm; FPGA performance; fabrication methodology; manufacturing yield; physical size; physical-design issues; power consumption; resource utilization; Computer science; Costs; Fabrication; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Logic design; Manufacturing; Power generation economics; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
ISSN :
1063-0988
Print_ISBN :
0-7803-2707-1
Type :
conf
DOI :
10.1109/ASIC.1995.580726
Filename :
580726
Link To Document :
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