Title :
An efficient selftimed adder design
Author :
Ramachandran, Ravi ; Lu, Shih-Lien
Author_Institution :
LSI Logic Corp., Milpitas, CA, USA
Abstract :
Existing adders use a horizontal carry propagation scheme to converge to a sum. Horizontal carry propagation inhibits the exploitation of the potential parallelism inherent in the process of addition. By using a vertical carry propagation scheme and self timing, this parallelism can be easily exploited. In the work presented here, we examine one such vertical boolean scheme for carry propagation and its implementation using self timing. The average speed of a n-bit adder thus implemented approaches O(log n) and has a hardware complexity of only O(n)
Keywords :
adders; carry logic; logic design; parallel architectures; timing; carry elimination adder; hardware complexity; n-bit adder speed; parallelism exploitation; self timing; self-timed adder design; vertical boolean scheme; vertical carry propagation scheme; Arithmetic; Delay; Design engineering; Equations; Hardware; Investments; Large scale integration; Logic design; Parallel processing; Timing;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580736
