A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems

Author

Kuo, J.B. ; Lou, J.H. ; Su, K.W.

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1995

fDate

18-22 Sep 1995

Firstpage

315

Lastpage

317

Abstract

This paper presents a high-speed 1.5 V clocked BiCMOS dynamic latch, which is derived from a clocked CMOS dynamic latch and a BiCMOS logic gate using BiPMOS pull-down structure, and a bootstrapped pull-up structure, for BiCMOS dynamic pipelined digital logic systems. Based on the study, for driving a load capacitance of 2 pf, the 1.5 V clocked BiCMOS dynamic latch provides a 2.5× improvement in switching time as compared to the clocked CMOS one

Keywords

BiCMOS logic circuits; VLSI; flip-flops; pipeline processing; transient analysis; 1.5 V; 2 pF; BiCMOS dynamic pipelined digital logic VLSI systems; BiCMOS logic gate; BiPMOS pull-down structure; bootstrapped pull-up structure; clocked CMOS dynamic latch; high-speed clocked BiCMOS latch; load capacitance; switching time; transient waveforms; BiCMOS integrated circuits; CMOS digital integrated circuits; CMOS logic circuits; Capacitance; Clocks; Latches; Logic circuits; Logic gates; Switching circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580739

Filename

580739