Title :
High performance single chip dataflow processor
Author_Institution :
Dept. of Res. & Dev., Northern Electr. Telekomunikasyon A.S., Istanbul, Turkey
Abstract :
A new dataflow concept, Multiple Input Node, is introduced to overcome the performance and efficiency degradation problems that exist in the current dataflow computation models. Multiple Input Node is a new computation node which has 4 inputs, hence it can accept up to 4 token packets at a time. The unique architecture of the Multiple Input Node reduces the number of token packets in the system and therefore increases performance. Also introduced is a newly designed dataflow processor architecture, Multiple Input Node Dataflow Processor, which utilizes the Multiple Input Node concept. The processor also has RISC based design, 4 stage pipeline architecture, peak performance of 120 MIPS, and a direct matching scheme. The architecture has been realized as a single chip ASIC by using European Silicon Structures 0.7 micron CMOS standard cell process
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; data flow computing; microprocessor chips; parallel architectures; pipeline processing; reduced instruction set computing; 0.7 micron; 120 MIPS; CMOS standard cell process; European Silicon Structures; RISC based design; dataflow computation models; dataflow processor architecture; direct matching scheme; four-stage pipeline architecture; multiple input node; single chip ASIC; single chip dataflow processor; Application specific integrated circuits; Computational modeling; Computer architecture; Counting circuits; Degradation; Multiprocessing systems; Parallel processing; Pipelines; Process design; Reduced instruction set computing;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580746
