Title :
A 109.5mW 1.2V 600M texels/s 3-D graphics engine
Author :
Imai, Masayoshi ; Nagasaki, Takeshi ; Sakamoto, J. ; Takeuchi, H. ; Nagano, Hidehisa ; Iwasaki, Shoichi ; Hatakenaka, M. ; Fujita, J. ; Motomura, T. ; Ueda, Toshitsugu ; Niki, T. ; Tomikawa, H.
Author_Institution :
Res. Center, Sony Corp., Yokohama, Japan
Abstract :
A 3D graphics engine consists of a programmable floating-point geometry engine and a rasterization engine to adapt to various memory-based set associative cache mechanism. The IC achieves 4.7M vertex/s and 600M texel /s systems, the rasterization engine has a coordinate I and dissipates 109.5mW. A 0.18 μm 5M CMOS process is used to implement the 25.4mm2 IC operating at 1.2V.
Keywords :
CMOS memory circuits; computer graphic equipment; coprocessors; floating point arithmetic; image texture; low-power electronics; 1.2 V; 109.5 mW; 3D graphics engine; CMOS process; alpha blending; alpha testing; clock distribution; depth testing; fast floating multiply-accumulate unit; flexible memory system; geometric operations; low power; memory-based set associative cache mechanism; pixel generation; programmable floating-point geometry engine; rasterization engine; system-dependent block; texture blending; triangle setup; trilinear texture mapping; Arithmetic; Character generation; Clocks; Computer graphics; Coprocessors; Energy consumption; Engines; Mobile handsets; Registers; Testing;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332729
