Variations on the theme for designing fault-tolerant systolic array architectures

An approach is presented for designing highly reliable and optimal fault-tolerant systolic array architectures. Redundant computations are introduced in the original algorithm by creating different versions of the algorithm. In these methods, the spatial redundancy technique is used to achieve fault tolerance in the fault-tolerant systolic architectures. The schemes can tolerate all single permanent and temporary faults in the array and a majority of the multiple fault patterns