Title :
A 3.6 Gb/s/pin simultaneous bidirectional (SBD) I/O interface for high-speed DRAM
Author :
Jae-Kwan Kim ; Jung-Hwan Choi ; Chan-Kyong Kim ; Woo-Seop Kim ; Changhyun Kim ; Soo-In Cho
Author_Institution :
Samsung Electron., Hwasung, South Korea
Abstract :
A point-to-point I/O interface for high-speed DRAM is described. The interface utilizes simultaneous bidirectional signaling that enables transmitting/receiving data through a line at the same time. The test scheme is implemented in 0.10 μm DRAM process. It achieves 3.6 Gb/s/pin in SBD mode and an I/O cell consumes 35 mW.
Keywords :
DRAM chips; data communication; integrated circuit testing; network interfaces; network topology; 0.10 micron; 3.6 Gbit/s; 35 mW; DRAM process; I/O cell power consumption; SBD mode; high-speed DRAM; point-to-point I/O interface; simultaneous bidirectional I/O interface; simultaneous bidirectional signaling; simultaneous data transmission/reception; test scheme; Bandwidth; Circuit testing; Circuit topology; Driver circuits; Impedance; Random access memory; Resistors; Sampling methods; Voltage control; Wire;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332770
