Title :
Size analysis of multilevel RRAM array and optimization of device and circuit characteristics
Author :
Ye-Xin Deng ; Peng Huang ; Bing Chen ; Xiao-lin Yang ; Bin Gao ; Li-Feng Liu ; Jin-Feng Kang ; Xiao-yan Liu
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
Multilevel RRAM array is one of the most promising candidates of next generation high density memory technology. In this paper, we investigate the size limitation of multilevel 1D1R RRAM array based on circuit simulation. Optimization of device characteristics and operation mode is obtained to increase the array size and the circuit performance. This work may be helpful for multilevel array design and application.
Keywords :
circuit optimisation; circuit simulation; random-access storage; circuit simulation; multilevel 1D1R RRAM array; optimization; size analysis; size limitation; Arrays; Circuit simulation; Degradation; Integrated circuit modeling; Next generation networking; Optimization; Resistance;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467605
