Title :
Multi-Gigabit I/O Link Circuit Design Challenges and Techniques
Author :
Wu, Zuoguo Joe ; Zou, Peng ; Dibene, J. Ted, II ; Yeung, Evelina ; Thenus, Fenardi
Author_Institution :
Intel Corp., Santa Clara
Abstract :
This paper describes the major challenges in designing multi-gigabit I/O link CMOS circuits. Techniques to overcome the challenges are presented, including transceiver design, discrete and continuous time equalization, termination control, and clocking circuits.
Keywords :
CMOS integrated circuits; integrated circuit design; CMOS circuits; clocking circuits; continuous time equalization; multigigabit I/O link circuit design; termination control; transceiver design; Bandwidth; Circuit synthesis; Clocks; Electrostatic discharge; Integrated circuit interconnections; Jitter; Reflection; Resistors; Threshold voltage; Timing;
Conference_Titel :
Electromagnetic Compatibility, 2007. EMC 2007. IEEE International Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-1349-4
Electronic_ISBN :
1-4244-1350-8
DOI :
10.1109/ISEMC.2007.99
