DocumentCode
3416807
Title
Impact of the pattern layout on radio-frequency performance of thin-film SOI power MOSFETs
Author
Matsumoto, Satoshi ; Mino, Masato
Author_Institution
NTT Energy & Environ. Syst. Labs., Atugi-Shi, Japan
fYear
2004
fDate
24-27 May 2004
Firstpage
245
Lastpage
248
Abstract
This paper describes guidelines for designing thin-film SOI power MOSFETs for linear-amplification applications. The linear-amplification characteristics and DC performance depend on the grand interconnection pattern. We prefer to put the grand pattern on the drain (output) side. There are optimum finger lengths which provide the best linear amplification characteristics. Finger length also depends on the operating frequency and total gate width.
Keywords
interconnections; power MOSFET; silicon-on-insulator; thin film transistors; MOSFET RF performance; drain side pattern; finger length optimization; gate width; grand interconnection pattern; linear-amplification; power MOSFET pattern layout effects; thin-film SOI power MOSFET; Power MOSFETs; Silicon on insulator technology; Thin film transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD '04. The 16th International Symposium on
Print_ISBN
4-88686-060-5
Type
conf
DOI
10.1109/ISPSD.2004.1332911
Filename
1332911
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