DocumentCode :
3417146
Title :
DVB-T synchronizer architecture design and implementation
Author :
Adiono, Trio ; Cahyadi, Willy Anugrah ; Salman, Amy Hamidah
Author_Institution :
Electr. Eng. Dept., Bandung Inst. of Technol., Bandung, Indonesia
Volume :
02
fYear :
2009
fDate :
5-7 Aug. 2009
Firstpage :
594
Lastpage :
599
Abstract :
This paper presents the design of synchronizer hardware for DVB-T receiver. The main function of synchronizer is to detect and compensate the time offset and frequency offset which happen during transmission as well as frame start detection. Proposed synchronizer utilizes cyclic prefix of OFDM signals. The design includes computational bit precision modeling, architecture design, register-transfer-level (RTL) codes implementation, and final synthesis into FPGA. The synthesis result shows that the synchronizer can satisfy the required specification of at least more than 40 MHz clock speed, i.e., specifically 55 MHz clock setup.
Keywords :
OFDM modulation; compensation; digital video broadcasting; field programmable gate arrays; synchronisation; digital video broadcasting-terrestrial; field programmable gate arrays; orthogonal frequency division multiplexing; register-transfer-level; time offset compensation; Clocks; Digital video broadcasting; Field programmable gate arrays; Frequency synchronization; Hardware; Informatics; OFDM; Oscillators; Signal synthesis; Timing; DVB-T; OFDM; WiMAX; cyclic prefix; register-transfer-level; synchronizer;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Engineering and Informatics, 2009. ICEEI '09. International Conference on
Conference_Location :
Selangor
Print_ISBN :
978-1-4244-4913-2
Type :
conf
DOI :
10.1109/ICEEI.2009.5254747
Filename :
5254747
Link To Document :
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