FPGA Implementation ofFDTD Algorithm

We examined the implementation of the FDTD algorithm to a Field Programmable Gate Array (FPGA) to accelerate an electromagnetic field simulation. We evaluate the calculation error of a fixed-point arithmetic using the FDTD method and show that the error of less than 0.01 is achieved when the bit length is greater than 28 bits. This paper investigates a method for shortening the time required for the FDTD calculation using the FPGA employing a 32-bit operation machine. First, the architecture of the FPGA hardware is described. Next, an analysis of the processing time for an unaltered FPGA implementation is described. We show that the time required to access an external memory for the FPGA becomes a dominant factor in the processing time because the calculation time is decreased due to parallel pipeline processing. We focus on reducing the number of data reads from the DDR memory and examine techniques to shorten the required time. We show that these techniques reduce the calculation time to 1/22 compared to the time required by one PC using commercial software, with the error of less than 0.01 compared to a floating point arithmetic.