DocumentCode :
3418018
Title :
High-performance scheduling algorithm for partially parallel LDPC decoder
Author :
Cheng-Zhou Zhan ; Xin-Yu Shih ; An-Yeu Wu
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
fYear :
2008
fDate :
March 31 2008-April 4 2008
Firstpage :
3177
Lastpage :
3180
Abstract :
In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partially parallel LDPC architecture is commonly used for reducing the area cost of the processing units. The dependency of two kinds of processing units, check node unit (CNU) and bit node unit (BNU), should be considered to enhance the hardware utilization efficiency (HUE). Based on the properties of the parity check matrix of LDPC codes, the updating calculation of the CNU and BNU can be overlapped to reduce the decoding latency by enhancing the HUE with the matrix scheduling algorithm. By applying our proposed LDPC scheduling algorithm to a (1944, 972)-irregular LDPC code, we can get about 60% throughput gain in average without any performance degradation.
Keywords :
decoding; matrix algebra; message passing; parity check codes; scheduling; bit node unit; check node unit; hardware utilization efficiency; low-density parity check code; overlapped message passing decoding; parity check matrix; partially parallel LDPC decoder; scheduling algorithm; Costs; Decoding; Degradation; Delay; Hardware; Message passing; Parity check codes; Performance gain; Scheduling algorithm; Throughput; LDPC; matrix; overlapped; partially-parallel; scheduling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Acoustics, Speech and Signal Processing, 2008. ICASSP 2008. IEEE International Conference on
Conference_Location :
Las Vegas, NV
ISSN :
1520-6149
Print_ISBN :
978-1-4244-1483-3
Type :
conf
DOI :
10.1109/ICASSP.2008.4518325
Filename :
4518325
Link To Document :
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