The economic benefits of new stepper technology for manufacturing with 0.35 μm IC design rules

An analysis is made of the economic benefits of stepper technology for manufacturing ICs with 0.35-μm design rules. A table of design rules required for manufacturing 0.35-μm ICs is proposed. With reference to these design rules, three critical budgets, CD control, overlay, and particulate control, are analyzed with respect to cost per critical layer and impact on cumulative yield using the SEMATECH cost of ownership model. The influence of major throughput parameters, alignment time, step time, and exposure time on cost per critical level and throughput is also modeled. The study led to a better understanding of the required stepper performance to obtain acceptable yields and throughput levels for cost effective manufacturing with 0.35-μm design rules. The model is also useful for understanding the significant productivity impact small changes in alignment time and step time can have and for measuring the actual economic benefit of further increasing lamp intensity