A secondary synchronization signal detection implementation for LTE downlink on a multi-core processor platform

Author

Xueqiu Yu ; Maofei He ; Zhiyi Yu ; Xiaoyang Zeng

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

This paper presents an implementation for secondary synchronization signal (SSS) detection in LTE downlink based on a multi-core processor platform. In LTE initial cell search procedure, the SSS is used for cell-identity group detection and 10 ms frame timing. The multi-core processor platform is a mesh array consists of SIMD (Single Instruction Multiple Data) cores. Thanks to its programmability and reconfigurability, the multi-core processor platform is well suited for wireless communication applications. An implementation of SSS detection with the throughput of 105.9 Mbps is achieved by deeply excavating the task-level parallelism among several cores and mapping based on route-length-minimized principle, which shows the advantage of multi-core processor platform.

Keywords

Long Term Evolution; cellular radio; multiprocessing systems; parallel processing; radio links; signal detection; telecommunication computing; LTE downlink; LTE initial cell search procedure; SIMD; cell-identity group detection; mesh array; multicore processor platform; route-length-minimized principle; secondary synchronization signal detection; single instruction multiple data core; wireless communication; Correlation; Downlink; Multicore processing; Synchronization; Throughput; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467765

Filename

6467765