Title :
A Low Power High Density Double Edge Triggered Flip Flop for Low Voltage Systems
Author :
Tiwari, Satish Chandra ; Singh, Kunwar ; Gupta, Maneesha
Author_Institution :
Adv. Electron. Lab., NSIT, New Delhi, India
Abstract :
The paper introduces a new low power, high density double edge triggered, (DET) flip-flop. The proposed DET flip-flop is implemented using lesser number of transistors as compared to other state of the art double edge triggered flip-flops designs. Simulation at 250MHz frequency using 180nm/1.8V CMOS technology with BSIM 3v3 parameters, the proposed design shows an improvement of upto 58.63%, 55.7% and 39.9% in terms of power dissipation, power delay product and total transistor width respectively. At scaled voltages, the power consumption of the proposed design reduces by 34% and hence the design is suitable for low power, low voltage and high density applications.
Keywords :
CMOS logic circuits; flip-flops; logic design; low-power electronics; power consumption; BSIM 3v3 parameters; CMOS technology; DET flip-flop; art double edge triggered flip-flops designs; low power high density double edge triggered flip flop; low voltage systems; power consumption; power delay product; power dissipation; total transistor width; Clocks; Delay; Flip-flops; Power dissipation; Transistors; Very large scale integration; Voltage control; Flip-Flops; VLSI; low voltage; power delay product;
Conference_Titel :
Advances in Recent Technologies in Communication and Computing (ARTCom), 2010 International Conference on
Conference_Location :
Kottayam
Print_ISBN :
978-1-4244-8093-7
Electronic_ISBN :
978-0-7695-4201-0
DOI :
10.1109/ARTCom.2010.64
