DocumentCode :
3420827
Title :
Compilation for Delay Impact Minimization in VLIW Embedded Systems
Author :
Ayala, José L. ; Atienza, David ; Raghavan, Praveen ; López-Vallejo, Marisa ; Catthoor, Francky
Author_Institution :
Dpto. de Ingenieria Electronica, Univ. Politecnica de Madrid
fYear :
2006
fDate :
Jan. 2006
Firstpage :
83
Lastpage :
90
Abstract :
Tomorrow´s embedded devices need to run high-resolution multimedia as well as need to support multi-standard wireless systems which require an enormous computational complexity with a very low energy consumption and very high performance constraints. In this context, the register file is one of the key sources of power consumption and performance bottleneck, and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new compilation approach to mitigate the performance implications of technology variation in the shared register file in upcoming embedded VLIW architectures with several processing units. The compilation approach is based on a redefined register assignment policy and a set of architectural modifications to this device. Experimental results show up to a 67% performance improvement with our technique
Keywords :
embedded systems; multiprocessing systems; program compilers; VLIW embedded systems; compilation; delay impact minimization; register assignment; register file; Computational complexity; Delay; Embedded computing; Embedded system; Energy consumption; Energy management; High performance computing; Multimedia systems; Registers; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Innovative Architecture for Future Generation High Performance Processors and Systems, 2006. IWIA '06. International Workshop on
Conference_Location :
Kohaha Coast, HI
ISSN :
1537-3223
Print_ISBN :
0-7695-2689-6
Type :
conf
DOI :
10.1109/IWIAS.2006.25
Filename :
4089359
Link To Document :
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