Nonlinear state observer for sequential logic circuits

The authors design an observer for nonlinear discrete-time systems and apply it to estimating the internal state of sequential logic circuits, i.e., the state of flip-flops (FFs). The logic circuit is modeled as a continuous-valued discrete-time nonlinear dynamical system. It is a collection of memories and neurons with the sigmoidal function, corresponding respectively to FFS and logic gates (AND, OR, etc.). The correction of the observed state of the logic circuit is derived based on the steepest descent method and the observer framework of the control theory. A simulation result on the estimation of the state of a simple sequential logic circuit is presented