High speed V.32 trellis encoder/decoder implementation using FPGA

Trellis-coded modulation is used in V.32 modems in order to obtain higher noise immunity than uncoded transmission at the same data rate, transmission power and bandwidth limit. Input data is grouped into 4-bit symbols and encoded into 5-bit symbols before being modulated and sent over a noisy channel to the receiver. A Viterbi decoder is used at the receiver to reconstruct the original data using soft-decision algorithm. By using a combination of parallel processing and pipelining, a high speed V.32 trellis encoder/decoder has been developed using a single FPGA. The encoder/decoder provides a 180 Mbit/s data rate that is more than a 1000× improvement compared to an equivalent digital signal processing implementation on a TMS320C5x DSP