Recursive maximum likelihood decoder for high-speed satellite communication

A decoder of (64,35) Reed-Muller subcode has been implemented, dedicatedly for high-speed satellite communication. The trellis-based recursive maximum likelihood decoding algorithm, which greatly reduces the computational costs of the conventional Viterbi algorithm, can be performed on a single chip by using 3-stage pipeline architecture of an add-compare-select (ACS) tree. By using 0.6 μm CMOS triple-metal technology, the (64,35) decoder integrates totally 160,023 gates into a 151.3 mm² die and operates at 60 MHz. The 600 Mbps (64,40) decoding system required for satellite communication can be constructed by employing 32 proposed decoders in parallel