Title :
An improved desynchronizer with reduced waiting time jitter for digital TDM systems
Author :
Ruan, Angela Q. ; Englefield, C.G. ; Goud, P.A.
Author_Institution :
Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
Abstract :
A new desynchronizer (or clock recovery circuit) for reducing waiting time jitter in TDM systems is described. The initial results indicate that this new method of clock recovery can give a significant reduction (approximately 50% for most DS-1 frequency offsets) in both the peak-to-peak and the r.m.s. waiting time jitter, as compared to the method currently used. With optimization of the system, further improvement should be possible
Keywords :
digital communication systems; phase-locked loops; time division multiplexing; clock recovery circuit; desynchronizer; differential PLL; digital TDM systems; waiting time jitter reduction; Bit rate; Clocks; Control systems; Digital filters; Frequency synchronization; Phase locked loops; Pulse circuits; Time division multiplexing; Timing jitter; VHF circuits;
Conference_Titel :
Communications, Computers and Signal Processing, 1991., IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
0-87942-638-1
DOI :
10.1109/PACRIM.1991.160738
