Comparative evaluation of gap-fill dielectrics in shallow trench isolation for sub-0.25 /spl mu/m technologies

Author

Nag, S. ; Chatterjee, A. ; Taylor, K. ; Ali, I. ; O´Brien, S. ; Aur, S. ; Luttmer, J.D. ; Chen, I.C.

Author_Institution

Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

841

Lastpage

845

Abstract

The dielectric material used to fill trenches in Shallow Trench Isolation (STI) of transistors, is key to device performance. This paper (a) evaluates the integration of currently available dielectric technologies and (b) designs an optimized process scheme for 0.25 /spl mu/m node and beyond. A detailed study of LPCVD TEOS, SACVD oxide, Hydrogen-Silsesquioxane SOG (HSQ) and ICP (Inductively Coupled) HDP (High Density Plasma) CVD oxide, for STI, is presented for the first time. A novel ICP HDP-CVD process scheme is shown to have the advantages of single step, low thermal budget and high throughput as well as provide good gap-fill, low HF etch rate, low moisture uptake, low shrinkage with annealing, low diode reverse leakage and isolation at 0.3 /spl mu/m spacing.

Keywords

CVD coatings; dielectric thin films; isolation technology; plasma CVD coatings; 0.25 micron; ICP HDP CVD oxide; LPCVD TEOS; SACVD oxide; gap-fill dielectric; hydrogen-silsesquioxane SOG; process optimization; shallow trench isolation; Design optimization; Dielectric materials; Etching; Hafnium; Isolation technology; Plasma applications; Plasma density; Plasma devices; Process design; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.554111

Filename

554111