A floating-gate technology for digital CMOS processes

We discuss the possibility of developing high-quality floating-gate memories and circuits in digital CMOS technologies that have only one layer of polysilicon. Here, the primary concern is whether or not we can get adequate control-gate linearity from MOS capacitors. We employ two experimental procedures to address this issue and find acceptable floating-gate circuit behaviour with MOS capacitors. First, we simultaneously characterize an MOS capacitor and a linear capacitor; the experimental data show that MOS capacitors behave similarly to linear capacitors over a finite, but usable range. Second, we characterize two typical floating-gate MOS circuit primitives, a floating-gate amplifier and a multiple-input translinear element, two basic circuits that rely heavily on the linearity of the capacitors that couple into the floating gates. Our measurements show that floating-gate circuits with MOS-capacitor control gates behave like their counterparts built with linear capacitors over specific regions of operation