• DocumentCode
    342467
  • Title

    Error neutralisation in switched current memory cells

  • Author

    Hughes, John B. ; Moulding, Kenneth W.

  • Author_Institution
    Imperial Coll. of Sci., Technol. & Med., London, UK
  • Volume
    2
  • fYear
    1999
  • fDate
    36342
  • Firstpage
    460
  • Abstract
    This paper demonstrates that high performance operation of switched-current memory cells can be achieved by neutralisation of the cell´s errors using gate-drain capacitive feedback. Simulation indicates that this technique can achieve 9-10 bit performance at a sampling frequency of 100 MS/s
  • Keywords
    analogue storage; circuit feedback; circuit simulation; error correction; switched current circuits; 9 to 10 bit; circuit simulation; error neutralisation; gate-drain capacitive feedback; sampling frequency; switched current memory cells; Capacitors; Circuits; Educational institutions; Feedback; Frequency; Laboratories; MOSFETs; Parasitic capacitance; Sampling methods; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
  • Conference_Location
    Orlando, FL
  • Print_ISBN
    0-7803-5471-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.1999.780770
  • Filename
    780770
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=342467