Verification and management of a multimillion-gate embedded core design

Author

Notbauer, Johann ; Albrecht, Thomas ; Niedrist, Georg ; Rohringer, Stefan

Author_Institution

Siemens Austria, Vienna, Austria

fYear

1999

fDate

1999

Firstpage

425

Lastpage

428

Abstract

Verification is one of the most critical and time-consuming tasks in today´s design processes. This paper demonstrates the verification process of a 8.8 million gate design using HW-simulation and cycle simulation-based HW/SW-coverification. The main focuses are overall methodology, testbench management, the verification task itself and defect management. The chosen verification process was a real success: the quality of the designed hardware and software was increased and furthermore the time needed for integration and test of the design in the context of the overall system was greatly reduced

Keywords

configuration management; embedded systems; formal verification; hardware-software codesign; reduced instruction set computing; ASIC; RISC processors; cycle simulation-based HW/SW-coverification; defect management; hardware-simulation; message buffer hardware; multimillion-gate embedded core design; multiple-processor platform; testbench configuration management; verification process; virtual platform; Application specific integrated circuits; Hardware; Operating systems; Packaging; Permission; Process design; Real time systems; Reduced instruction set computing; Switches; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings. 36th

Conference_Location

New Orleans, LA

Print_ISBN

1-58113-092-9

Type

conf

DOI

10.1109/DAC.1999.781353

Filename

781353