High-order syndrome testing for VLSI circuits

This paper, based on the well-known syndrome testing, introduces some new concepts of so called high-order syndrome testing for VLSI circuits to improve the efficiency of the method. Syndrome testing has been developed for years in the areas of testing. It is known that the syndrome testing is one of the exhaustive ways of testing, which could be one of the main barriers to widespread acceptance of the exhaustive way of testing since it could be time-consuming when the number of input variables is growing. In this paper, a novel concept called partial syndrome testing is presented in which the traditional syndrome is divided into several parts such that it contains at least two advantages comparing to that of traditional one: (1) increasing the fault coverage and (2) reducing the testing time, therefore, to improve the efficiency of the testing. Procedure of deriving the partial syndrome is described in detail. Experimental results on benchmark as well as other circuits are also given to evaluate the performances of this new approach.