DocumentCode
3429136
Title
Fault Localization and Full Error Correction in Radix2 Signed Digit-Based Adders
Author
Alavi, Seyyed Roohollah ; Faez, Karim
Author_Institution
Islamic Azad Univ. Qazvin, Qazvin
fYear
2007
fDate
22-24 Aug. 2007
Firstpage
214
Lastpage
218
Abstract
In this paper, a new methodology to increase fault-tolerant and full error correction capabilities in self-checking adders based on the radix 2 signed digit (SD) representation is presented. The full error correction ability is indebted to "locality" property of carry propagation in this type of adder, in which the carry propagation is confined to neighbor digits. The second motive of using these adders is their computational speed. In fact, because the parity of the augends is preserved, the error produced by a single stuck-at fault can be detected by parity checker. As "locality" property of carry propagation prevents dissemination of error yielded by permanent faults, therefore, the location of faulty digit is found by using a recomputation with shifted operands method. Finally, after fault localization, the full error correction is performed by using a recomputation with triple shifted operands method.
Keywords
adders; digital arithmetic; error correction; fault location; fault tolerance; carry propagation; fault localization; fault tolerance; full error correction; radix 2 signed digit-based adders; selfchecking adders; stuck-at fault; Arithmetic; Books; Computer architecture; Error correction; Fault detection; Fault tolerance; Process design; Semiconductor device reliability;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Computers and Signal Processing, 2007. PacRim 2007. IEEE Pacific Rim Conference on
Conference_Location
Victoria, BC
Print_ISBN
978-1-4244-1189-4
Electronic_ISBN
1-4244-1190-4
Type
conf
DOI
10.1109/PACRIM.2007.4313214
Filename
4313214
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