Title :
Systolic VLSI compiler (SVC) for high performance vector quantisation chips
Author :
Hu, Y. ; McCanny, J.V. ; Yan, M.
Author_Institution :
Dept. of Electr. & Electron. Eng., Queen´´s Univ. of Belfast, UK
Abstract :
An overview is given of a systolic VLSI compiler (SVC) tool currently under development for the automated design of high performance digital signal processing (DSP) chips. Attention is focused on the design of systolic vector quantization chips for use in both speech and image coding systems. The software in question consists of a cell library, silicon assemblers, simulators, test pattern generators, and a specially designed graphics shell interface which makes it expandable and user friendly. It allows very high performance digital coding systems to br rapidly designed in VLSI
Keywords :
VLSI; circuit layout CAD; computerised picture processing; digital signal processing chips; encoding; systolic arrays; CAD; DSP chip; automated design; cell library; circuit layout tool; digital coding systems; graphics shell interface; high performance vector quantisation chips; image coding systems; overview; silicon assemblers; simulators; speech coding systems; systolic VLSI compiler; systolic vector quantization chips; test pattern generators; Digital signal processing chips; Image coding; Signal design; Silicon; Software libraries; Software systems; Speech coding; Static VAr compensators; Vector quantization; Very large scale integration;
Conference_Titel :
Application Specific Array Processors, 1990. Proceedings of the International Conference on
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-9089-5
DOI :
10.1109/ASAP.1990.145451
