Abstract :
The objective of this paper is to present a specific EEPROM functional fault model related to the impact of bridging faults in the array of cells. Moreover, the evolution of these functional faults throughout the useful life of the memory is established. In this aim, a hierarchical overview from the array structure down to the floating gate transistor simulation model is given. A set of bridging faults is defined with their corresponding stimuli. Finally, a representative simulation example is detailed.
