Title :
Analysis of timing jitter in CMOS ring oscillators
Author :
Weigandt, Todd C. ; Kim, Beomsup ; Gray, Paul R.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
30 May-2 Jun 1994
Abstract :
in this paper the effects of thermal noise in transistors on timing jitter in CMOS ring-oscillators composed of source-coupled differential resistively-loaded delay cells is investigated. The relationship between delay element design parameters and the inherent thermal noise-induced jitter of the generated waveform are analyzed. These results are compared with simulated results from a Monte-Carlo analysis with good agreement. The analysis shows that timing jitter is inversely proportional to the square root of the total capacitance at the output of each inverter, and inversely proportional to the gate-source bias voltage above threshold of the source-coupled devices in the balanced state. Furthermore, these dependencies imply an inverse relationship between jitter and power consumption for an oscillator with fixed output period. Phase noise and timing jitter performance are predicted to improve at a rate of 10 dB per decade increase in power consumption
Keywords :
CMOS digital integrated circuits; digital phase locked loops; integrated circuit noise; jitter; oscillators; phase noise; synchronisation; thermal noise; timing circuits; CMOS ring oscillators; Monte-Carlo analysis; PLL; capacitance; delay element design parameters; fixed output period; gate-source bias voltage; phase noise; power consumption; resistively-loaded delay cells; source-coupled differential delay cells; thermal noise; timing jitter; Analytical models; Capacitance; Delay effects; Energy consumption; Inverters; Noise generators; Propagation delay; Ring oscillators; Thermal resistance; Timing jitter;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409188