Power Reduction in VLIW Processor with Compiler Driven Bypass Network

With the increase in issue width, bypass control of a processor become more complex. Also, in a processor, operands are read both from register file as well as from bypass. For a multi-port register file, read/write energy is much more than that of single port register file. Both redundant register read/write and bypass control area can be reduced with compiler hints for register bypass. In this work we suggest an innovative way to represent compiler bypass hints that serve both these motivations. Further, bypass hints are used in effective design of multi-stage bypass network. Experiments on media-bench benchmarks show that by using our approach: (i) register file energy savings can be as much as 60%; (ii) and synthesis of VLIW core saves 2-4% of the core area