Polysilicon resistive heated scribe lane test structure for productive wafer level reliability monitoring of NBTI

Author

Muth, Werner ; Martin, Andreas ; Von Hagen, Jochen ; Smeets, David ; Fazekas, Josef

Author_Institution

Infineon Technol. AG, Munich, Germany

fYear

2003

fDate

17-20 March 2003

Firstpage

155

Lastpage

160

Abstract

A polysilicon resistive heated test structure was designed with a MOSFET embedded between two polysilicon heater stripes. A 4-terminal metal resistor above the heaters allows temperature control via the temperature coefficient of the resistance. A stress algorithm performs simultaneous thermal and electrical stress. The real device temperature is gained by a comparison of the temperature measured at the metal level and the pn-junction temperature measured by the forward diode characteristics. Bias Temperature Instability stress results from this structure are presented.

Keywords

MOSFET; semiconductor device measurement; semiconductor device reliability; semiconductor device testing; temperature measurement; thermal stresses; MOSFET; NBTI; electrical stress; forward diode characteristics; heater stripes; negative bias temperature instability; pn-junction temperature; polysilicon resistive heated test structure; productive wafer level reliability monitoring; scribe lane test structure; temperature coefficient; temperature control; thermal stress; Electrical resistance measurement; Gain measurement; MOSFET circuits; Monitoring; Niobium compounds; Resistors; Temperature measurement; Testing; Thermal stresses; Titanium compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2003. International Conference on

Print_ISBN

0-7803-7653-6

Type

conf

DOI

10.1109/ICMTS.2003.1197440

Filename

1197440