Title :
Optimize WIP scale through simulation approach with WIP, turn-over rate and cycle time regression analysis in semiconductor fabrication
Author_Institution :
UMC, Hsinchu, Taiwan
Abstract :
In a foundry semiconductor fabrication the goal of achieving maximum profits is maximizing the wafer out target on a premise of acceptable cycle time. This paper presents and applies a methodology for determining the optimal WIP scale of an IC manufacturing fab. From the simulation result obtained, we experimentally confirmed that there is a positive correlation between WIP and Cycle Time, negative correlation between WIP and turn-over rate. Further, we built a second-order regression model for WIP and wafer out correlation, and obtained an absolute maximum wafer out volume based on an acceptable WIP level.
Keywords :
electronics industry; integrated circuit manufacture; optimisation; production control; regression analysis; work in progress; IC manufacturing; WIP level; cycle time regression; optimal WIP; second order regression; semiconductor fabrication; simulation; turn over rate; wafer out correlation; wafer out target; Analytical models; Cities and towns; Discrete event simulation; Fabrication; Foundries; Predictive models; Production facilities; Regression analysis; Semiconductor device modeling; Semiconductor process modeling;
Conference_Titel :
Semiconductor Manufacturing Technology Workshop, 2002
Print_ISBN :
0-7803-7604-8
DOI :
10.1109/SMTW.2002.1197452
