The multistable memory effect in accumulation mode SOI MOSFETs at low temperatures

The multistable V_T behavior of silicon-on-insulator (SOI) MOSFETs is considered. This phenomenon, the MCCM (multistable charge controlled memory) effect, was first found in non-fully depleted SOI n-MOSFET samples operating at 77 K when negative back gate bias V_G2 was applied. When the applied V_G2 was swept from zero-voltage towards a negative value, e.g. -40 V, the V_T of the front gate would shift higher with rather good linearity within a V_G2 span of about 20-30 V. The increase in V_T can be up to 2-3 V. The MCCM effect is only related to the coupling between the front and the back gates and does not depend on whether there are junctions or a potential well in the body. All the transistors investigated operate in the non-fully depleted regime for both high and low states at both room and low temperatures. The measurement results show that such multi-stable V_T behavior also occurs in the N⁺N^-N⁺ accumulation mode SOI n-MOSFETs