Title :
An improved comparison circuit for low power pre-computation-based content-addressable memory designs
Author :
Pai, Yu-Ting ; Lee, Chia-Han ; Ruan, Shanq-Jang ; Naroska, Edwin
Author_Institution :
Dept. of Electron. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
Abstract :
This paper proposes a CMOS comparison architecture for low-power pre-computation-based content-addressable memory (PB-CAM). Instead of conventional architecture, we implement ours by CMOS logic gates to eliminate power consumption induced by short-circuit current. We use TSMC 0.18-¿m techfile to estimate the power consumption by Synopsys Nanosim. The width ratio between PMOS and NMOS is set as 3:1. This ratio can effectively reduce both rise time and fall time, thereby reducing the delay for each comparison cycle. Compare with static pseudo-nMOS CAM word circuit, this architecture can save 50.2% power consumption on average.
Keywords :
CMOS logic circuits; CMOS memory circuits; comparators (circuits); logic gates; low-power electronics; short-circuit currents; CMOS comparison architecture; CMOS logic gates; Synopsys Nanosim; low-power content-addressable memory; pre-computation-based content-addressable memory; short-circuit current; static pseudo-nMOS CAM word circuit; Buffer storage; CADCAM; CMOS logic circuits; CMOS technology; Computer aided manufacturing; Design engineering; Energy consumption; MOS devices; Mechanical engineering; Power engineering and energy; Associative Memory; CAM; Logic-Gate; Low power;
Conference_Titel :
Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on
Conference_Location :
Yasmine Hammamet
Print_ISBN :
978-1-4244-5090-9
Electronic_ISBN :
978-1-4244-5091-6
DOI :
10.1109/ICECS.2009.5410806