DocumentCode :
3434327
Title :
Determination of generation lifetime in silicon-on-insulator (SOI) substrates using a three-terminal capacitance-time response
Author :
McDaid, L.J. ; Hall, S. ; Eccleston, W. ; Alderman, J.C.
Author_Institution :
Dept. of Electr. Eng. & Electron., Liverpool Univ., UK
fYear :
1990
fDate :
2-4 Oct 1990
Firstpage :
93
Lastpage :
94
Abstract :
Capacitance-voltage (C-V) and capacitance-time ( C-T) measurements used to yield valuable material parameters in thin-film silicon-on-insulator MOS capacitors are considered. The authors previously demonstrated (1989) that a two-terminal C-V can yield the thickness of the body (silicon overlayer) and the buried oxide. However, a more comprehensive assessment of SOI material necessitates the evaluation of the generation lifetime in the body region, as this quantity directly correlates with leakage current and is crucial in determining parasitic effects such as lateral bipolar action in SOI transistors. It is shown that the minority carrier generation lifetime can be obtained by monitoring the capacitance between the gate and substrate after the application of a step voltage
Keywords :
carrier lifetime; metal-insulator-semiconductor devices; minority carriers; semiconductor-insulator boundaries; SOI MOS capacitors; Si-SiO2; body region; capacitance-voltage measurements; lateral bipolar action; minority carrier generation lifetime; parasitic effects; three-terminal capacitance-time response; Body regions; Capacitance measurement; Capacitance-voltage characteristics; DC generators; Leakage current; MOS capacitors; Monitoring; Parasitic capacitance; Semiconductor thin films; Silicon on insulator technology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOS/SOI Technology Conference, 1990., 1990 IEEE
Conference_Location :
Key West, FL
Print_ISBN :
0-87942-573-3
Type :
conf
DOI :
10.1109/SOSSOI.1990.145725
Filename :
145725
Link To Document :
بازگشت