ViSiMIPS: Visual simulator of MIPS32 pipelined processor

Pipelining is a very important implementation technique in computer architecture which permits several instructions to be executed simultaneously, each of them in a different stage of the datapath. Students of computer science need to acquire this fundamental concept clearly but most of them find it unfathomable. Moreover, it is difficult for an instructor to teach these concepts on a paper and pencil basis. In this paper, we present ViSiMIPS, which simulates and dynamically visualizes the processing of instructions by MIPS32 pipelined processor to assist in teaching such concepts. In addition, it describes details of the basics of MIPS instruction set and pipelining, also designates ViSiMIPS, its main components and functionalities. Its graphical user interface (GUI) illustrates the register-transfer level and expedites students to comprehend the different stages of pipelining.