Title :
The efficient design of a strongly fault-secure ALU using a reduced Berger code for WSI processor arrays
Author :
Kim, J.H. ; Rao, T.R.N. ; Feng, G.L. ; Lo, J.-C.
Author_Institution :
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Layfayette, LA, USA
Abstract :
Due to their operative nature, arithmetic and logic units (ALUs) are the most difficult functional circuits to check among the components of a processor. The efficient design of a 32-b strongly-fault-secure (SFS) ALU using a reduced Berger code is presented. The reduced Berger code encodes both operands and the computation results, and uses only the two least significant check bits of its Berger code counterpart regardless of information length. The application of reduced Berger code yields more efficient implementation of a strongly-fault-secure ALU than the previously proposed techniques.
Keywords :
VLSI; fault tolerant computing; microprocessor chips; 32 bits; WSI processor arrays; computation results; functional circuits; information length; least significant check bits; operands; reduced Berger code; strongly fault-secure ALU; Arithmetic; Circuit faults; Computer errors; Electrical fault detection; Integrated circuit technology; Logic circuits; Microprocessors; Process design; Real time systems; Very large scale integration;
Conference_Titel :
Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0867-0
DOI :
10.1109/ICWSI.1993.255262
