Millimeter-Waves building block design methodology in BiCMOS technology

Focusing on circuit routing which is a very critical design step in mm-Waves range, this work proposes a systematic modeling of layout parasitic elements thus fitting measurement and simulation results. Scalable models of extra-device routing elements based on 3D EM software simulations are developed. Two building blocks are so designed and implemented in a 130 nm BiCMOS technology. A two stage cascode LNA which achieves a power gain of 21.14 dB at 61.5 GHz, -21.2 dBm input compression point and a noise figure of 4.3 dB at 60 GHz. The core of the circuit consumes 10.2 mW under 1.2 V. The 64 GHz push-push oscillator operating under 1.8 V, 22 mA, performs a output power of -14 dBm at 68 GHz, the tuning range is about 4 GHz from 64 GHz to 68 GHz.