Design of High-Speed Charge-Pump in PLL

Author

Wu Xiu-long ; Chen Jun-ning ; Ke Dao-Ming ; Zhang Xing-Jian

Author_Institution

Inst. of Electron. Sci. & Technol., Anhui Univ., Hefei

fYear

2008

fDate

12-14 Oct. 2008

Firstpage

1

Lastpage

3

Abstract

The phenomena of charge injection, clock feedthrough and charge sharing in charge pump are analyzed. A novel structure of charge pump for high-speed phase-locked loop is presented. The charge pump is designed with the Chartered 0.35 mum CMOS technology, and simulated with Eldo which is the analog circuits simulation tool of Mentor Graphics. Under 3.3 V DC supply voltage, the power consumption is 0.447 mW. The result of simulation shows that the circuit has an excellent performance for high-frequency applications.

Keywords

CMOS analogue integrated circuits; charge pump circuits; phase locked loops; CMOS technology; DC supply voltage; Eldo analog circuits simulation tool; PLL; charge injection; charge sharing; clock feedthrough; high-speed charge-pump; phase-locked loop; power 0.447 mW; power consumption; size 0.35 mum; voltage 3.3 V; Analog circuits; CMOS analog integrated circuits; CMOS technology; Charge pumps; Circuit simulation; Clocks; Graphics; Phase locked loops; Power supplies; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications, Networking and Mobile Computing, 2008. WiCOM '08. 4th International Conference on

Conference_Location

Dalian

Print_ISBN

978-1-4244-2107-7

Electronic_ISBN

978-1-4244-2108-4

Type

conf

DOI

10.1109/WiCom.2008.555

Filename

4678463