High voltage DMOS power FETs on thin SOI substrates

Author

O´Connor, J.M. ; Luciani, V.K. ; Caviglia, A.L.

Author_Institution

Allied-Signal Aerosp. Co., Columbia, MD, USA

fYear

1990

fDate

2-4 Oct 1990

Firstpage

167

Lastpage

168

Abstract

A 90 V, 1.3 A double-diffused MOS (DMOS) power FET fabricated on a 400 nm thick SOI (silicon-on-insulator) film is reported. By utilizing thin SOI materials, these devices can be easily integrated with analog and digital devices to form smart power monolithic circuits. The power devices can be isolated from each other and from the control circuitry by either etching or oxidizing (local oxidation of silicon) through the thin SOI layer, and both high and low side drivers can be combined on a single chip. The thin SOI layer virtually eliminates step coverage problems with interconnects and avoids complicated planarization schemes often needed for dielectrically isolated power devices

Keywords

MOS integrated circuits; integrated circuit technology; power integrated circuits; semiconductor-insulator boundaries; 1.3 A; 400 nm; 90 V; DMOS; control circuitry; double-diffused MOS; etching; high side drivers; low side drivers; oxidizing; power FET; smart power monolithic circuits; thin SOI substrates; Driver circuits; Etching; FETs; Integrated circuit interconnections; Oxidation; Planarization; Semiconductor films; Silicon on insulator technology; Substrates; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOS/SOI Technology Conference, 1990., 1990 IEEE

Conference_Location

Key West, FL

Print_ISBN

0-87942-573-3

Type

conf

DOI

10.1109/SOSSOI.1990.145765

Filename

145765